ILP-based board-level routing of multi-terminal nets for prototyping reconfigurable interconnect

被引:0
|
作者
Kirschbaum, A [1 ]
Becker, J [1 ]
Glesner, M [1 ]
机构
[1] Darmstadt Univ Technol, Inst Microelect Syst, Darmstadt, Germany
来源
VLSI: SYSTEMS ON A CHIP | 2000年 / 34卷
关键词
reconfigurable interconnect; rapid-prototyping; board-level routing; ILP-model;
D O I
暂无
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
For the board-level routing of intermodule connections with reprogrammable devices in a prototyping environment we present an Integer Linear Programming (ILP) model. It is solvable in polynomial time for architectures consisting of two routing devices even for multi-terminal nets. A net decomposition strategy is presented to handle all remaining infeasible problems. In contrast to previous work this approach allocates a minimum of additional port resources and thus significantly improves the routability of multi-terminal net dominated designs.
引用
收藏
页码:659 / 670
页数:12
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