Transistor-based electrical test structures for lithography and process characterization

A multi-student testchip aimed at characterizing lithography related variations with over 15,000 individually probable test structures and transistors has been designed and a complementary 65nm process flow and data aggregation strategy have also been implemented. Test structures have been strategically designed to have high sensitivities to non-idealities such as defocus, LWR, misalignment and other systematic sources of variation. To enable automated measurement of massive amounts of test structures, Enhanced Transistor Electrical CD (Critical Dimension) metrology has been used as it offers high pattern density and almost no geometrical restrictions. Electrical testing at cryogenic temperatures will be employed to study the impact of Line Width Roughness (LWR) versus Random Dopant Fluctuations (RDF), which will not play a significant role at cryogenic temperatures, 4K. To facilitate data analysis and comparison of results between students, a relational database has been designed and implemented. The database will be web accessible for each student to use and update. It will serve as a collaborative platform for reinforcing conclusions, filtering out confounding data, and involving outside parties that are interested in process variations at the 65nm node. Experimental data was not available at the time this paper was written, so this paper will concentrate on the design and simulation results of test structures.