A 19-bit Range and 4.5-ps Resolution Fully-Synthesizable Time-to-Digital Converter with Quad-Edge Offset Cancellation

被引：0

作者：

Cheong, Heon Hwa ^{[1
,2
]}

Kim, Suhwan ^{[1
]}

机构：

[1] Seoul Natl Univ, Dept Elect & Comp Engn, Seoul, South Korea

[2] Samsung Elect, Memory Business Div, Suwon, South Korea

来源：

2022 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 22) | 2022年

关键词：

offset cancellation; synthesizable; standard library cell; cyclic Vernier; time-to-digital converter; PS RESOLUTION; LOCKED LOOP; TDC; PLL;

D O I：

10.1109/ISCAS48785.2022.9937646

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This presents a fully-synthesizable cyclic Vernier time-to-digital converter (TDC) which cancels the offsets by a quad-edge offset cancellation (QOC) scheme. The system delays its internal clocks and uses the clock offsets to compensate for many types of offsets altogether, which includes the wiring mismatches, the duty cycle skews, and the long-term jitters of the clocks. During calibration, the QOC-TDC measures the offsets of the clock paths. The measured offsets are then canceled in the normal mode. An additional scheme of coarse-fine boundary synchronization further enhances the output monotonicity. Consisting of only standard library cells offering fully-automated implementation, the QOC-TDC achieves a 19bit range, a 4.5-ps resolution, and the throughput of 22MS/s, while drawing 3.4mW from a 1.0V supply, as shown by the postlayout simulations in 28nm CMOS.

引用

页码：3378 / 3382

页数：5