VLSI architectures for computing exponentiations, multiplicative inverses, and divisions in GF(2(m))

A modified parallel-in-parallel-out linear-systolic power-sum circuit designed to perform AB(2) + C computations in the finite field GF(2(m)) is presented, where A, B, and C are arbitrary elements of GF(2(m)), On the basis of the linear-systolic power-sum circuits, a VLSI architecture for exponentiation in GF(2(m)) is developed, Furthermore, two modified architectures that can be used to compute inverses and divisions over GF(2(m)) are proposed, All the architectures are constructed from m 1 linear-systolic power-sum circuits, It should be noted that the presented exponentiator, inverter, and divider are the only such circuits having a throughput of 100%, The latency of the presented pipeline exponentiator, inverter, and divider is m(m - 1) clock cycles, The cycle time (i.e., clock period) of the presented architectures is only two logic gate delays plus a short routing delay, For moderate values of m, say m less than or equal to 10, the circuit complexity of the presented circuits is realizable using presently available VLSI technology, The computation time of near two gate delays and 100% throughput enables the greatest computation speed in finite field arithmetic.