The readout driver for the ATLAS muon end-cap trigger and its architecture and design language techniques

The prototype of the Read Out Driver for the ATLAS Muon Endcap trigger system is described. The hardware is based on a single large Xilinx Virtex FPGA that accepts data from four gigabit optical links and sends processed output to the ATLAS central DAQ via an S-link and sampled data to a VME processor via the VMEbus. A C-like procedural language was used for a large part of the design. In addition to using pipelined logic and other standard FPGA design techniques, the design uses some architectural elements that are more common in microprocessor architectures. The ROD's design features, implementation details, DAQ software, experience with the procedural language and performance are described.