Data driven VLSI computation for low power DCT-based video coding

The paper presents a VLSI architecture for the low-power and low-complexity implementation of 2D discrete cosine transform and its inverse (DCT/IDCT) in video coding applications. A circuit based on the Chen algorithm and the distributed arithmetic approach is described. Since DCT/IDCT coefficients are typically quite small we use a data driven clock gating strategy to turn off some portions of the circuit when operating on input data equal to zero or whose most significant bits are just sign extensions. For typical H.263/MPEG video coding applications this approach provides 26% and 36% power reduction in the DCT and IDCT modes, respectively.