Analytical modelling and performance analysis of gate engineered TG silicon-on-nothing metal-oxide-semiconductor field-effect transistor

被引：3

作者：

Banerjee, Pritha ^{[1
]}

Saha, Priyanka ^{[1
]}

Sarkar, Subir K. ^{[1
]}

机构：

[1] Jadavpur Univ, Dept Elect & Telecommun Engn, Kolkata 700032, India

来源：

IET CIRCUITS DEVICES & SYSTEMS | 2018年 / 12卷 / 05期

关键词：

SHORT-CHANNEL; SOI MOSFETS; THRESHOLD VOLTAGE; SIMULATION; SPEED;

D O I：

10.1049/iet-cds.2017.0473

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This study presents a three-dimensional (3D) analytical model of triple material tri-gate silicon-on-nothing metal- oxide-semiconductor field-effect transistor. The performance of the device by varying the different device parameters as well as the device's immunity toward the various short channel effects such as Drain-induced barrier lowering (DIBL), hot carrier effect, threshold-voltage roll-off and subthreshold swing are investigated. The 3D Poisson's equation with appropriate boundary conditions is solved considering the parabolic potential approximation method to obtain the surface potential distribution. In addition, the calculations for threshold voltage and electric field are also done and the results obtained are verified using a 3D device simulator, namely ATLAS from SILVACO.

引用

页码：557 / 562

页数：6

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