FPGA IMPLEMENTATION OF EFFICIENT FIR FILTER WITH QUANTIZED FIXED-POINT COEFFICIENTS

被引：0

作者：

Bhalke, Santosh ^{[1
]}

Manjula, B. M. ^{[1
]}

Sharma, Chirag ^{[1
]}

机构：

[1] Nitte Menakshi Inst Technol, Dept Elect & Commun Engn, Bangalore, Karnataka, India

来源：

2013 INTERNATIONAL CONFERENCE ON EMERGING TRENDS IN COMMUNICATION, CONTROL, SIGNAL PROCESSING AND COMPUTING APPLICATIONS (IEEE-C2SPCA-2013) | 2013年

关键词：

FIR filter; Carry-Select Adder; Carry-Look-ahead Adder; Multiplier; Modified Booth Algorithm; FSM;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Finite Impulse Response (FIR) Filters is a digital filter which is used in digital signal processing like communicate-on, biomedical signal processing, image processing, etc. These Digital filters are used to filter out the part of signal that is redundant or damages the original signal. In this paper we have implemented a design of digital FIR filter using Finite State Machine (FSM). In this approach it is possible to reuse the hardware implemented so that the area will be reduced significantly, and also the delay and power will be reduces as compared to the MATLAB - Simulink based FIR Filters. In this design the filter coefficients used are fixed-point coefficients, which will reduce the truncation and computation complexity.

引用

页数：5

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