Parallel implementation of motion-compensation for HDTV video decoder

被引:1
|
作者
Lee, CL [1 ]
机构
[1] Ind Technol Res Inst, Comp & Commun Res Labs, Chutung 310, Taiwan
关键词
D O I
10.1109/ISCE.1997.658349
中图分类号
TP [自动化技术、计算机技术];
学科分类号
0812 ;
摘要
A parallel motion compensation architecture is proposed for HDTV video decoder. It is based on the block layer picture partitioning. It adds a routing module between decoding engines and block layer memory modules. It can resolve memory access conflicts and avoid extra access delay. The simultaneous access and identical addressing properties make the control scheme very simple. The routing network can be implemented by a simple interconnection network. This architecture is applicable to macroblock structures of 4:2:0, 4:2:2 and 4:4:4 chroma formats. This architecture can be one of the solution for parallel HDTV video decoder.
引用
收藏
页码:51 / 54
页数:4
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