Investigation of tri-gate hetero-junction stacked dielectric transistor for improved ON-current

Three different work functions are taken in this paper for investigating a hetero-junction tri gate tunnel FET and it is simulated using TCAD. The proposed device employs hetero-junction structure that exhibits lesser band-gap between source and intrinsic region, which leads to the improvement in On-current. Three lengths (L1, L2 and L3) are taken and the performance of the device is analyzed by considering the depletion regions of the source, channel and drain. From the simulation, parameters like drain current, surface potential, electrical field in vertical and lateral directions are obtained. Four regions are allocated in this device and are examined with different hetero-structures; materials and the model prophesy the electrostatic potential accurately. Improvisation in ON-current (10(-5)A) is also achieved when comparing to the performance analysis carried out using Triple Material Tri-gate TFET without a stack structure. The accuracy and characteristics of the device are evaluated using TCAD simulation. (C) 2019 Elsevier Ltd. All rights reserved. Selection and Peer-review under responsibility of the scientific committee of the 2nd International Conference on Nanoscience and Nanotechnology.