Design and Characterization of a 9.2-Gb/s Transceiver for Automotive Microcontroller Applications With 8-Taps FFE and 1-Tap Unrolled/4-Taps DFE

被引：4

作者：

Bandiziol, Andrea ^{[1
]}

Grollitsch, Werner ^{[1
]}

Steffan, Giovanni ^{[1
]}

Nonis, Roberto ^{[1
]}

Palestri, Pierpaolo ^{[2
]}

机构：

[1] Infineon Technol, Design Enabling & Syst, A-9500 Villach, Austria

[2] Univ Udine, Polytech Dept Engn & Architecture, I-33100 Udine, Italy

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2018年 / 65卷 / 10期

关键词：

Serial-links; automotive; high-speed; equalization; inter-symbol interference; CMOS TECHNOLOGY; SERIAL LINK;

D O I：

10.1109/TCSII.2018.2850148

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We have designed a high-speed serial interface operating at 9.2 Gb/s for an automotive microcontroller in a 28-nm planar CMOS technology. The full-rate voltage-mode transmitter features an 8-tap feed-forward equalization where each tap can be programmed with steps of 1/16. Impedance tuning is possible by activating different driver replicas. The halfrate receiver features continuous time-linear equalization as well as decision-feedback equalization with 4 taps (one loop-unrolled), along with a dedicated phase-detection algorithm. The final circuit occupies an area of 0.125 mm(2) and consumes 5.7 mW/Gb/s under nominal conditions. Experimental characterization demonstrates that the equalization strategies are able to improve the bit error rate well below 10(-12) with typical communication channels for automotive applications.

引用

页码：1305 / 1309

页数：5

共 5 条

[1] Automotive-Range Characterization of a 11 Gb/s Transceiver for Automotive Microcontroller Applications with 8-Tap FFE, 1-Tap Unrolled/3-Tap DFE and Offset-Compensated Samplers
D'Ampolo, Dylan
Bandiziol, Andrea
Menin, Davide
Grollitsch, Werner
Nonis, Roberto
Palestri, Pierpaolo
2019 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2019), 2019, : 225 - 228
[2] Design of a half-rate receiver for a 10Gbps automotive serial interface with 1-tap-unrolled 4-taps DFE and custom CDR algorithm
Bandiziol, Andrea
Grollitsch, Werner
Brandonisio, Francesco
Bassi, Matteo
Nonis, Roberto
Palestri, Pierpaolo
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[3] Design and Simulation of a 12 Gb/s Transceiver With 8-Tap FFE, Offset-Compensated Samplers and Fully Adaptive 1-Tap Speculative/3-Tap DFE and Sampling Phase for MIPI A-PHY Applications
Menin, Davide
Bandiziol, Andrea
Grollitsch, Werner
Nonis, Roberto
Palestri, Pierpaolo
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (08) : 1369 - 1373
[4] An 18-Gb/s NRZ Transceiver With a Channel-Included 2-UI Impulse-Response Filtering FFE and 1-Tap DFE Compensating up to 32-dB Loss
Ahn, Cheolmin
Hong, Jaehyeong
Shin, Jongshin
Kim, Byungsub
Park, Hong-June
Sim, Jae-Yoon
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS, 2020, 67 (12) : 2863 - 2867
[5] A 0.3pJ/bit 112Gb/s PAM4 1+0.5D TX-DFE Precoder and 8-tap FFE in 14nm CMOS
Toifl, T.
Menolfi, C.
Braendli, M.
Cevrero, A.
Francese, P. A.
Kossel, M.
Kull, L.
Luu, D.
Morf, T.
Ozkaya, I
2018 IEEE SYMPOSIUM ON VLSI CIRCUITS, 2018, : 53 - 54

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