Analysis of multiple sampling technique for digitally controlled dc-dc converters

Digitally controlled switching mode power supplies (SMPS) exhibit bandwidth limitations imposed by the switching frequency, the nonzero delay response of the controller, the calculation delays in the control algorithm and the analog-to-digital conversion times. An additional bandwidth limitation comes from the operation of the digital pulse width modulator (DPVM). When employed in a sampled data system, PWM modulation introduces additional phase lag in the control loop, which turns out to be dependent on the steady-state duty cycle. Multiple sampling technique seems promising in reducing the sampling and modulator phase lag and ultimately achieving higher control bandwidth. In this paper the multiple sampling concept and analytical modeling are discussed, as well as the major drawbacks that come from the increased sampling frequency. Some provisions for the elimination of the state variable ripple are also proposed. Simulation and experimental results are provided to validate our assessments.