NBTI in dual gate oxide PMOSFETs

被引：7

作者：

Chaparala, P ^{[1
]}

Brisbin, D ^{[1
]}

Shibley, J ^{[1
]}

机构：

[1] Natl Semicond Corp, Adv Proc Technol Dev, Santa Clara, CA 95052 USA

来源：

2003 8TH INTERNATIONAL SYMPOSIUM ON PLASMA- AND PROCESS-INDUCED DAMAGE | 2003年

关键词：

D O I：

10.1109/PPID.2003.1200942

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In advanced analog and mixed signal applications, Negative Bias Temperature Instability (NBTI) in dual gate oxide (DGO) technologies poses significant challenges for process development and robust analog circuit design. In this paper, Vt mismatch shift due to NBTI in a cascode current mirror is examined. The impact of stress time, temperature, gate voltage, drain voltage, and annealing on NBTI degradation is investigated over wide range of stress conditions. Proper process trade-offs must be made to reduce NBTI degradation while integrating a DGO module into a high performance CMOS core process.

引用

页码：138 / 141

页数：4

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