On-chip implementation of a multi-output voltage regulator based on single inductor Buck Converter topology

This paper presents the chip design of a single inductor triple output buck converter with interleaved switched capacitor outputs with only the passive elements being off-chip. Transient overshoots occur in all the output voltages during load transients due to cross regulation effect amongst the coupled outputs. This has been minimized using a priority based novel control technique. The error amplifiers are designed accordingly. The dead band circuitry amongst the output switches have been optimally designed so that the power MOSFET's do not breakdown at the instance when all the output switches are momentarily turned OFF Moreover, selection of the size of the power switches has been a significant contribution as their stray capacitances are used to hold the voltage across the power switches during dead band condition. The chip has been implemented on 1.5u process following DSL specifications. The post layout simulation results are presented in the paper and they all prove the stable operation of the circuit and the validation of the stated theories.