VALID: Custom ASIC verification and FPGA education platform

被引：1

作者：

Murphy, P ^{[1
]}

Frantz, JP ^{[1
]}

Welsh, E ^{[1
]}

Hardy, R ^{[1
]}

Mohsenin, T ^{[1
]}

Cavallaro, J ^{[1
]}

机构：

[1] Rice Univ, Houston, TX 77251 USA

来源：

2003 IEEE INTERNATIONAL CONFERENCE ON MICROELECTRONIC SYSTEMS EDUCATION, PROCEEDINGS | 2003年

关键词：

D O I：

10.1109/MSE.2003.1205257

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes VALID, a platform for testing student designed ASICs and for teaching the basics of FPGA design. VALID is designed to maximize ease of use from a student's perspective while maintaining enough flexibility for its use as an FPGA development and instruction platform. This system was designed entirely by students, has been successfully manufactured and is currently, being used in a number of courses at Rice.

引用

页码：64 / 65

页数：2

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