Measurements and Simulation of Self-Heating in 40 nm SOI MOSFETs

被引：2

作者：

Zhang, Xiong ^{[1
]}

Mehr, Payam ^{[1
]}

Vasileska, Dragica ^{[1
]}

Thornton, Trevor ^{[1
]}

机构：

[1] Arizona State Univ, Sch ECEE, Tempe, AZ 85287 USA

来源：

2021 5TH IEEE ELECTRON DEVICES TECHNOLOGY & MANUFACTURING CONFERENCE (EDTM) | 2021年

关键词：

Self-heating effect (SHE); silicon-on-insulator (SOI); CMOS; modeling and simulation; THERMAL-CONDUCTIVITY;

D O I：

10.1109/EDTM50988.2021.9421023

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

To understand self-heating in SOI CMOS, conventional and trap-rich substrates are used to fabricate 40nm gate length NFET pairs that share the same active region. One NFET serves as a heater, while the other is used as a calibrated thermometer. Measurements of the local heating confirm the simulated temperature distribution. Heat flow out of the metal contacts reduces the self-heating in NFETs on trap-rich substrates which have reduced thermal conductivity compared to conventional SOI wafers.

引用

页数：3

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