A real-time high performance edge detector for computer vision applications

We present a high performance edge detection architecture for real-time image processing applications. The architecture is finely pipelined. The proposed ASIC is capable of producing one edge-pixel every clack cycle. At a clock rate of 10 MHz, the architecture can process 30 frames per second, where the size of each frame is 640x480 8-bit pixels. The ASIC was laid out and fabricated using Samsung's 0.8 mu m double-metal CMOS process.