Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices

被引：0
|
作者：
Hirosaki, Akihiro [1 ]
Miura, Masatomo [1 ]
Matsumoto, Atsushi [1 ]
Hanyu, Takahiro [1 ]
机构：
[1] Tohoku Univ, Res Inst Elect Commun, Aoba Ku, 2-1-1 Katahira, Sendai, Miyagi 9808577, Japan
来源：
38TH INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC (ISMVL 2008) | 2008年
关键词：
D O I：
10.1109/ISMVL.2008.13
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A compensation method against a threshold-voltage (V-th) variation using tunneling magnetoresistive (TMR) devices, is proposed for a deep-submicron VLSI. The influence of the V-th variation in a single MOS transistor can be neglected by adjusting the source voltage of the MOS transistor. The desired circuit behavior is obtained by programming the resistance value of a TMR device which is connected to the MOS transistor in series. By using HSPICE simulation under a 90nm CMOS technology, it is demonstrated that a radix-2 signed-digit adder using the proposed method is robust against the V-th variation.
引用
收藏
页码：14 / 19
页数：6
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