The Study of FPGA-based Three-Level SVM NPC Inverter

In this paper, a scheme of FPAG-based three-level space vector modulation (SVM) inverter is proposed in details. Compared to the traditional two-level inverter, the three-level inverter using SVM control has superior performance though bringing about much computational complexity. Therefore, the FPGA-based implementation could solve this problem well. The SVM algorithm for three-level inverter is described, including the approach to calculate the dwell times of each switching state using volt-second characteristic, the algorithm of determining the space vector location and the principle for selecting switching sequences to generate symmetrical PWM output waves. The algorithm of determining the space vector location is derived from the mathematic idea of linear programming. The standard design flow of FPGA implementation and the functional block diagram of FPGA realization are given. The simulation model is constructed in the Mat lab/Simulink simulation environment in order to verify the correctness and feasibility of the three-level SVM algorithm.