Lattice-Based Cryptosystems on FPGA: Parallelization and Comparison Using HLS

被引:3
|
作者
Zijlstra, Timo [1 ]
Bigou, Karim [2 ]
Tisserand, Arnaud [3 ,4 ]
机构
[1] SERMA Safety & Secur Bordeaux, F-33600 Pessac, France
[2] Univ West Brittany, Lab STICC UMR 6285, F-29238 Brest, France
[3] CNRS, F-56321 Lorient, France
[4] Lab STICC UMR 6285 Lorient, F-56321 Lorient, France
关键词
Encryption; Field programmable gate arrays; Hardware; Public key; Optimization; Lattices; Costs; Learning with errors; post-quantum cryptography; public-key encryption; hardware implementation; high-level synthesis; CRYPTOGRAPHY; TRANSFORM; COMPACT;
D O I
10.1109/TC.2021.3112052
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
This paper deals with hardware implementations for lattice-based cryptography. Various CPA and CCA secure algorithms for LWE, RLWE and MLWE problems have been studied, parallelized, implemented and compared on FPGA using high-level synthesis. The impact of PRNG choices on the implementations performances and costs is also evaluated. HLS allows us to compare various sets of algorithms, architectures and parameters with a reduced design effort. Our results are often similar to state-of-the-art for various speed and cost trade-offs. Sometimes we obtain better results thanks to the exploration of numerous architecture and algorithm optimizations.
引用
收藏
页码:1916 / 1927
页数:12
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