Parallel 4x4 Transform on Bit Serial Shared Memory Architecture for H.264/AVC

被引：0
|
作者：
Rubin, Grzegorz [1 ]
机构：
[1] Bialystok Tech Univ, Dept Comp Sci, Bialystok, Poland
来源：
MIXDES 2009: PROCEEDINGS OF THE 16TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS | 2009年
关键词：
FPGA; shared memory; video coding;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
Many video applications require dedicated hardware to achieve acceptable levels of performance. H.264/AVC, the latest standard for video signal coding, utilizes a 4x4 integer transform to concentrate energy of residual data in a few coefficients. This paper presents an implementation and simulation of parallel 4x4 transform on bit serial shared memory architecture for H.264/AVC. Compared with the existing parallel implementations, the proposed architecture reduces interconnection resources of physical elements of FPGA device. The results of simulation show that the transform can be realized in real time on bit serial arithmetic.
引用
收藏
页码：675 / 680
页数：6
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