Manufacturability of 248nm phase shift lithography for 100nm transistors

The timing of 193nm tools and the resists to support them is driving semiconductor manufacturers to plan for production of sub-half lambda features on 248nm exposure tools. Lithographers are turning to reticle enhancements to close the capability gap, finding (as expected) that there are a myriad of issues that must be addressed to achieve production-worthiness. The current work describes efforts at Texas Instruments to extend 248nm lithography to 130nm and 100nm patterned features using strong phase-shift techniques. Focusing on the processes required for gate patterning, we show data demonstrating excellent process margin for devices with sub-100 nm gate lengths. Process capability tradeoffs such as dense-iso bias, depth of focus, exposure latitude, ultimate resolution, across chip linewidth variation and mask error factor (MEF) are discussed in detail with supporting data double dagger. Consistent with the findings of previous researchers, the characterization data to be presented show the process margin that can be achieved with these phase shifting techniques and their suitability for manufacturing. Clearly, process margin is not the entire picture. Motivated by the increased process complexity of phase shift lithography, we also investigate the logistical and business implications of using this technology for gate pattern. The impact of 248nm strong phase shift on Cost of Ownership as compared to a "traditional" 193nm binary process is explored in detail through the use of sensitivity analysis. The cost per wafer for lithography is evaluated as a function of key cost drivers such as throughput, tool cost, and process margin. As a result, we identify particular parameter spaces where 248nm strong phase shift processes are both lithographically and economically viable.