Wafer level reliability procedures to monitor gate oxide quality using V ramp and J ramp test methodology

被引：0

作者：

Lie, LN ^{[1
]}

Kapoor, AK ^{[1
]}

机构：

[1] LSI LOG CORP,MILPITAS,CA 95035

来源：

1995 INTERNATIONAL INTEGRATED RELIABILITY WORKSHOP, FINAL REPORT | 1996年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

引用

页码：113 / 121

页数：9

共 7 条

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[6] Off-line Wafer Level Reliability Control: Unique measurement method to monitor the lifetime indicator of gate oxide validated within Bipolar/CMOS/DMOS technology
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[7] Wafer-level characterization of EEPROM tunnel oxide using a fast floating-gate technique and a realistic memory cell-based test structure
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