Translation UML diagrams into Verilog

被引：20

作者：

Bazydlo, Grzegorz ^{[1
]}

Adamski, Marian ^{[1
]}

Stefanowicz, Lukasz ^{[1
]}

机构：

[1] Univ Zielona Gora, Zielona Gora, Poland

来源：

2014 7TH INTERNATIONAL CONFERENCE ON HUMAN SYSTEM INTERACTIONS (HSI) | 2014年

关键词：

UML; state machine diagram; logic controller; Hierarchical Concurrent Finite State Machine (HCFSM); Verilog; MICROPROGRAMMED CONTROLLERS; HYPERGRAPHS; REDUCTION; LENGTH;

D O I：

10.1109/HSI.2014.6860487

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

The paper presents a method of using the UML state machine diagrams for specification of programs of logic controllers. The proposed method allows transformation from UML state machine diagram, using temporal Hierarchical Concurrent Finite State Machine (HCFSM) model, into Verilog hardware specification. The generated behavioral description in Hardware Description Language can afterwards be simulated, synthesized and implemented into e.g. FPGA device. A practical example illustrating the successive stages of the proposed method was also presented.

引用

页码：267 / 271

页数：5

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