Application of a statistical design methodology to low voltage analog MOS integrated circuits

被引：0
|
作者：
Tarim, TUB [1 ]
Ismail, M [1 ]
机构：
[1] Texas Instruments Inc, Dallas, TX 75266 USA
来源：
ISCAS 2000: IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS - PROCEEDINGS, VOL IV: EMERGING TECHNOLOGIES FOR THE 21ST CENTURY | 2000年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The statistical design of the four-MOSFET structure and the 10-bit current division network is presented in this paper. The quantitative measure of the effect of mismatch between the transistors in both circuits is provided. Optimization of transistor W and L values. and yield enhancement are demonstrated. The circuits are fabricated through the MOSIS 2 mu m process using MOS transistor Level-3 model parameters. The experimental results are included in the paper.
引用
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页码：117 / 120
页数：4
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