Near-linear wirelength estimation for FPGA placement

With rapid advances in integrated circuit technology, wirelength has become one of the most critical and important metrics in all phases of VLSI physical design automation, especially circuit placement. As the precise wirelength for it given placement can only be known after routing, accurate and fast-to-compute wirelength estimates are required by FPGA placement algorithms. In this paper, a new model, called star+, is presented for estimating wirelength during FPGA placement. The proposed model is continuously differentiable and can be used with both analytic and iterative-improvement placement methods. Moreover, the time required to calculate incremental changes in cost incurred by moving/swapping blocks can always be computed in O(1) time. Results show that when incorporated into the well-known VPR framework and tested using the 20 MCNC benchmarks, the star+ model achieves a 6-9% reduction in critical-path delay compared with the half-perimeter wirelength (HPWL) model, while requiring roughly the same amount of computational effort.