Artificial Neural Network-Based Compact Modeling Methodology for Advanced Transistors

被引:86
|
作者
Wang, Jing [1 ]
Kim, Yo-Han [2 ]
Ryu, Jisu [2 ]
Jeong, Changwook [2 ]
Choi, Woosung [1 ]
Kim, Daesin [2 ]
机构
[1] Samsung Semicond Inc, DSA R&D, Device Lab, San Jose, CA 95134 USA
[2] Samsung Elect, Data & Informat Technol Ctr, Suwon 16677, South Korea
关键词
Integrated circuit modeling; Mathematical model; Field effect transistors; Training; Data models; Semiconductor device modeling; SPICE; Artificial neural network (ANN); circuit simulation; compact modeling; design-technology-cooptimization (DTCO); emerging devices; field-effect transistor (FET); machine learning; pathfinding; statistical modeling; MOSFET MODEL; DESIGN;
D O I
10.1109/TED.2020.3048918
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The artificial neural network (ANN)-based compact modeling methodology is evaluated in the context of advanced field-effect transistor (FET) modeling for Design-Technology-Cooptimization (DTCO) and pathfinding activities. An ANN model architecture for FETs is introduced, and the results clearly show that by carefully choosing the conversion functions (i.e., from ANN outputs to device terminal currents or charges) and the loss functions for ANN training, ANN models can reproduce the current-voltage and charge-voltage characteristics of advanced FETs with excellent accuracy. A few key techniques are introduced in this work to enhance the capabilities of ANN models (e.g., model retargeting, variability modeling) and to improve ANN training efficiency and SPICE simulation turn-around-time (TAT). A systematical study on the impact of the ANN size on ANN model accuracy and SPICE simulation TAT is conducted, and an automated flow for generating optimum ANN models is proposed. The findings in this work suggest that the ANN-based methodology can be a promising compact modeling solution for advanced DTCO and pathfinding activities.
引用
收藏
页码:1318 / 1325
页数:8
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