Integration of formal specification into the standard ASIC design flow

被引：1

作者：

Haas, W ^{[1
]}

Gossens, S ^{[1
]}

Heinkel, U ^{[1
]}

机构：

[1] Univ Erlangen Nurnberg, Inst Comp Aided Circuit Design, D-91052 Erlangen, Germany

来源：

7TH IEEE INTERNATIONAL SYMPOSIUM ON HIGH ASSURANCE SYSTEMS ENGINEERING, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/HASE.2002.1173122

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper presents our approach to leverage formal methods in an industrial design environment by closing the gap between the specification and design phases. We achieve this goal by, deriving behavioural VHDL models front a formal system specification in tabular form that is easily accessible to mathematical analysis.

引用

页码：189 / 194

页数：6

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