Via-programmable expanded universal logic gate in MCML for structured ASIC applications: Circuit design

被引：1
|
作者：
Brauer, Elizabeth J. [1 ]
Hatirnaz, I.
Badel, S.
Leblebici, Y.
机构：
[1] No Arizona Univ, Dept Elect Engn, Flagstaff, AZ 86011 USA
[2] Swiss Fed Inst Technol, Microelect Syst Lab, CH-1015 Lausanne, Switzerland
来源：
2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/ISCAS.2006.1693229
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper presents a via-programmable expanded universal logic gate in MOS Current-Mode Logic which can implement any 3-input Boolean function, and a significant subset of 4-input and 5-input functions. The universal logic gate is programmed with the first via mask, while Mcta13 and higher levels are used for cell-to-cell interconnections. Thus the cell is suitable for a structured ASIC design methodology. The circuit was used to create a functional cell library which can implement a wide range of functions. The cells are simulated to characterize delays, and a design strategy is proposed for large scale integration.
引用
收藏
页码：2893 / 2896
页数：4
相关论文
共 13 条
  • [1] Via-programmable structured ASIC fabric based on MCML cells: Design flow and implementation
    Badel, Stphane
    Hatirnaz, IlHan
    Leblebici, Yusuf
    Brauer, Elizabeth J.
    IEEE MWSCAS'06: PROCEEDINGS OF THE 2006 49TH MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS,, 2006, : 85 - +
  • [2] Implementation of structured ASIC fabric using via-programmable differential MCML cells
    Badel, Stephane
    Hatirnaz, Ilhan
    Leblebici, Yusuf
    Brauer, Elizabeth J.
    IFIP VLSI-SOC 2006: IFIP WG 10.5 INTERNATIONAL CONFERENCE ON VERY LARGE SCALE INTEGRATION & SYSTEM-ON-CHIP, 2006, : 234 - +
  • [3] The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3
    Hori, Ryohei
    Ueoka, Taisuke
    Otani, Taku
    Yoshikawa, Masaya
    Fujino, Takeshi
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [4] The implementation of DES circuit on via-programmable structured ASIC architecture VPEX3
    Hori, Ryohei
    Ueoka, Taisuke
    Otani, Taku
    Yoshikawa, Masaya
    Fujino, Takeshi
    2013 INTERNATIONAL SYMPOSIUM ON VLSI DESIGN, AUTOMATION, AND TEST (VLSI-DAT), 2013,
  • [5] Improved Via-Programmable Structured ASIC VPEX3 and Its Evaluation
    Hori, Ryohei
    Kitamori, Tatsuya
    Ueoka, Taisuke
    Yoshikawa, Masaya
    Fujino, Takeshi
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2012, E95A (09) : 1518 - 1528
  • [6] Via Programmable Structured ASIC Architecture "VPEX3" and CAD Design System
    Hori, Ryohei
    Ueoka, Taisuke
    Otani, Taku
    Yoshikawa, Masaya
    Fujino, Takeshi
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2012, E95A (12) : 2182 - 2190
  • [7] Design of Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit
    Sen, Bibhash
    Sengupta, Anik
    Dalui, Mamata
    Sikdar, Biplab K.
    53RD IEEE INTERNATIONAL MIDWEST SYMPOSIUM ON CIRCUITS AND SYSTEMS, 2010, : 1181 - 1184
  • [8] Design of Testable Universal Logic Gate Targeting Minimum Wire-Crossings in QCA Logic Circuit
    Sen, Bibhash
    Sengupta, Anik
    Dalui, Mamata
    Sikdar, Biplab K.
    13TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN: ARCHITECTURES, METHODS AND TOOLS, 2010, : 613 - 620
  • [9] Standard Cell Like Via-Configurable Logic Blocks for Structured ASIC in an Industrial Design Flow
    Tung, Hui-Hsiang
    Lin, Rung-Bin
    Li, Mei-Chen
    Heish, Tsung-Han
    IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (12) : 2184 - 2197
  • [10] Logic Block and Design Methodology for Via-Configurable Structured ASIC Using Dual Supply Voltages
    Lin, Ta-Kai
    Lin, Kuen-Wey
    Chiu, Chang-Hao
    Lin, Rung-Bin
    GLSVLSI'14: PROCEEDINGS OF THE 2014 GREAT LAKES SYMPOSIUM ON VLSI, 2014, : 111 - 116
12