Three-Dimensional Integration Technology Based on Self-Assembled Chip-to-Wafer Stacking

We have demonstrated that a number of known good dies (KGDs) can be precisely aligned in batch and stacked on LSI wafers by our chip-to-wafer three-dimensional (3D) integration technology using an innovative self-assembly technique. Compared with conventional robotic pick-and-place chip assembly, the fluidic self-assembly can provide high-throughput chip alignment and bonding, and the resulting self-assembled chips have high alignment accuracy of approximately 0.3 mu m on average. Immediately after chip release, the chips are aligned onto the predetermined hydrophilic bonding areas in a short time within 0.1 see by the surface tension of aqueous liquid used in our self-assembly. By using the self-assembly, a number of KGDs with different chip sizes, different materials and different devices can be stacked in high yield to give highly integrated 3D chips we call the 3D Super Chip.