Implementation of Scalable Interconnect Networks for data reordering used in Discrete Trigonometric Transforms (DTT)

被引:0
|
作者
Hussein, Adel [1 ]
Suleiman, Adnan [1 ]
Kerkiz, Nabil [2 ]
Akopian, David [1 ]
机构
[1] Univ Texas San Antonio, Dept Elect & Comp Engn, San Antonio, TX 78249 USA
[2] Intel Corp, Austin, TX USA
关键词
ARCHITECTURE; ALGORITHMS;
D O I
10.1109/ICICDT.2009.5166282
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The number of processing elements (PE) can be reduces significantly using partial column structure to perform Discrete Trigonometric Transform (DTT) computation. Data reordering is required between stages (columns). A scalable interconnect network for both global and local for data reordering is presented in this paper. The network scalability is based on the transform size and the number of processing elements (PE). The structure will reorder data on the fly and eliminate the need of memory. This will help evaluating throughput vs. complexity (cost and area.). Detail analysis of hardware cost will be presented
引用
收藏
页码:139 / +
页数:2
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