Parallel Multipliers for Quantum-Dot Cellular Automata

被引:25
|
作者
Kim, Seong-Wan [1 ]
Swartzlander, Earl E., Jr. [1 ]
机构
[1] Univ Texas Austin, Dept Elect & Comp Engn, Austin, TX 78712 USA
关键词
D O I
10.1109/NMDC.2009.5167566
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper explores the optimization of parallel multipliers for Quantum-Dot Cellular Automata. To reduce the complexity, multipliers are designed with quasi-modularity to accommodate large word sizes. The regular quasi-modular product method is used to make n x n multipliers using 4 (n/2 x n/2) modules. This may be continued with further decomposition to 16 (n/4 x n/4) modules, etc. The last two rows in Wallace or Dadda reduction trees are summed by an adder that is 3n/2 - 1 bits long to produce the final product. This design is constructed using coplanar layouts and compared with other QCA multipliers (bit-serial and array multipliers). The delay, area and complexity are compared for several different operand sizes using the QCADesigner simulator.
引用
收藏
页码:68 / 72
页数:5
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