A 0.6mW/Gbps, 6.4-8.0Gbps Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90nm CMOS

被引：0

作者：

Hu, Kangmin ^{[1
]}

Jiang, Tao ^{[1
]}

Wang, Jingguang ^{[1
]}

O'Mahony, Frank ^{[2
]}

Chiang, Patrick Yin ^{[1
]}

机构：

[1] Oregon State Univ, Sch Elect Engn & Comp Sci, Corvallis, OR 97331 USA

[2] Intel Corp, Hillsboro, OR 97124 USA

来源：

2009 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2009年

关键词：

Serial link; receiver; injection-locked oscillator;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper describes a quad-channel, 6.4-8Gbps serial link receiver testchip using a global forwarded clock distribution coupled to local injection-locked ring oscillators in 90nm CMOS. Each receiver consists of a low-power linear equalizer, four offset-cancelled quantizers for 1:4 demultiplexing, and an injection-locked ring oscillator for greater than one UI of phase deskew. Measured results show a 6.4-7.2Gbps data rate with BER < 10(-15) across 10cm of FR4 backplane, and 8.0Gpbs data rate with direct input. Designed in a 1.2V, 90nm CMOS process, the area of each receiver is 0.0174mm(2), with a measured power efficiency of 0.6mW/Gbps.

引用

页码：46 / +

页数：2