Investigation of Scaling and Temperature Effects in Total Ionizing Dose (TID) Experiments in 65 nm CMOS

被引：0

作者：

Chevas, Loukas ^{[1
]}

Nikolaou, Aristeidis ^{[1
]}

Bucher, Matthias ^{[1
]}

Makris, Nikolaos ^{[1
]}

Papadopoulou, Alexia ^{[1
]}

Zografos, Apostolos ^{[1
]}

Borghello, Giulio ^{[2
,4
]}

Koch, Henri D. ^{[3
,4
]}

Faccio, Federico ^{[4
]}

机构：

[1] Tech Univ Crete, Sch Elect & Comp Engn, Khania 73100, Greece

[2] Univ Udine, DPIA, I-33100 Udine, Italy

[3] Univ Mons, SEMi, B-7000 Mons, Belgium

[4] CERN, EP Dept, CH-1211 Geneva, Switzerland

来源：

PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM (MIXDES 2018) | 2018年

关键词：

Analog parameter; High Luminosity-Large Hadron Collider; ionizing radiation; MOSFET; total ionizing dose (TID);

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Ten-fold radiation levels are expected in the upgrade of the High-Luminosity Large Hadron Collider (HL-LHC) at CERN. Bulk silicon CMOS at 65 nm offers appreciable advantages among cost, performance, and resilience to high 'total Ionizing Dose (TID). In the present paper, geometrical scaling of key analog design parameters of MOS transistors irradiated at high TID is investigated. Experiments are carried out for TM of 100, 200 and up to 500 Mrad(SiO2) and at -30 degrees C, 0 degrees C, and 25 degrees C. We find that parameters are least degraded at -30 degrees C However, short-channel NMOSTs show a significant degradation of slope factor, which is more severe at 0 degrees C than at 25 degrees C. In contrast, the slope factor in short-channel PMOSTs shows lowest sensitivity to high TID.

引用

页码：313 / 318

页数：6

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