High-level design verification using Taylor Expansion Diagrams: First results

Recently a theory of a compact, canonical representation for arithmetic expressions, called Taylor Expansion Diagram (TED) [1] [2], has been proposed. This representation, based on a novel, non-binary decomposition principle, raises a level of design abstraction from bits to bit vectors and words, thus facilitating the verification of behavioral and RTL specifications of arithmetic designs. This paper presents the first practical results of using TED in the context of high-level design representation and verification. It discusses the use of TED for equivalence checking of behavioral and RTL designs and comments on its limitations. It also demonstrates the application of TEDs to verification of designs on algorithmic level and comments on their potential use in high level synthesis.