TEM study of iridium silicide contact layers for low Schottky barrier MOSFETs

An influence of annealing temperatures (300, 400 and 500 degrees C) on the iridium silicide formation in the Ir/Si structure was analysed by means of the transmission electron microscopy (TEM). The silicide layer is formed by the solid-state reaction between 15 nm thick Ir metallisation and a Si layer during the rapid-thermal-annealing (RTA) process for 120 s. The silicide layers are used as source/drain contacts for a novel technology of low Schottky barrier MOSFETs on SOL For this reason the high quality of the silicide/Si interface and the silicide structure are essential for the electrical properties of the device. The studies enabled the determination of the silicide layer thickness, the layer morphology, and the silicide/Si interface roughness as well as the identification of the silicide phase. Annealing of the Ir/Si structure at 300 and 400 degrees C caused formation of an amorphous iridium silicide layer between the iridium layer and the silicon substrate. At the highest annealing temperature (500 degrees C) the whole Ir layer completely reacted with Si, forming a crystalline iridium silicide layer. A diffraction analysis showed that the silicide layer consists of the dominant IrSi orthorhombic phase and another silicide phase with higher content of silicon (IrSix). The IrSix is placed between IrSi and Si. It indicates that during solid-state reaction at 500 degrees C the Si diffusion is predominant.