Modeling of UHF Voltage Multiplier for Radio-Triggered Wake-Up Circuit

被引:0
|
作者
Wang, Jiang [1 ]
Fu, Yuzhuo [1 ]
Dong, Liang [2 ]
机构
[1] Shanghai Jiao Tong Univ, Sch Microelect, Shanghai 200240, Peoples R China
[2] Western Michigan Univ, Dept Elect & Comp Engn, Kalamazoo, MI 49008 USA
关键词
DESIGN;
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An analytical model of an ultra-high frequency (UHF) voltage multiplier for the radio-triggered wake-up circuit is derived in this paper. The model is compliant with HSpice circuit simulations, and it allows for short design time of an optimal voltage multiplier. With low incident RF signal power, the optimal design of the voltage multiplier takes into account the number of stages of the multiplier, the diode saturation current and the emission coefficient, and the load impedance. We design and optimize a voltage multiplier with a matching depletion layer capacitance according to this model. With an RF input signal of 2.4 GHz and 200 nW, it can provide a constant dc output of 1 V within tens of microsecond.
引用
收藏
页码:108 / +
页数:2
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