Customization of application specific heterogeneous multi-pipeline processors

In this paper we propose Application Specific Instruction Set Processors with heterogeneous multiple pipelines to ef ciently exploit the available parallelism at instruction level. We have developed a design system based on the Thumb processor architecture. Given an application specified in C language, the design system can generate a processor with a number of pipelines specifically suitable to the application, and the parallel code associated with the processor Each pipeline in such a processor is customized, and implements its own special instruction set so that the instructions can be executed in parallel with low hardware overhead. Our simulations and experiments with a group of benchmarks, largely from Mibench suite, show that on average, 77% performance improvement can be achieved compared to a single pipeline A SIP, with the overheads of 49% on area, 51% on leakage power, 17% on switching activity, and 69% on code size.