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- [3] A novel SVPWM strategy considering DC-link balancing for a multi-level voltage source inverter [J]. APEC'99: FOURTEENTH ANNUAL APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION, CONFERENCE PROCEEDINGS, VOLS 1 & 2, 1999, : 509 - 514
- [4] Self-Balancing DC-link Capacitor Voltages in Seven-Level Inverter using Selective Harmonics Elimination PWM [J]. PROCEEDINGS OF THE 2016 IEEE 11TH CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS (ICIEA), 2016, : 922 - 927
- [5] DC-Link Capacitor Voltage Balancing using Redundant Vectors for Five-Level Neutral Point Clamped Voltage Source Inverter [J]. 2013 IEEE 14TH INTERNATIONAL VACUUM ELECTRONICS CONFERENCE (IVEC), 2013,
- [6] Five-level inverter scheme for an induction motor drive with simultaneous elimination of common-mode voltage and DC-link capacitor voltage imbalance [J]. IEE PROCEEDINGS-ELECTRIC POWER APPLICATIONS, 2005, 152 (06): : 1539 - 1555
- [9] DC Link Capacitor Voltage Balancing of a Dual Three-Level T-Type AC Drive Using Switching State Redundancy [J]. 2017 IEEE INTERNATIONAL ELECTRIC MACHINES AND DRIVES CONFERENCE (IEMDC), 2017,