A Unified Buffer Cache Architecture that Subsumes Journaling Functionality via Nonvolatile Memory

被引:16
|
作者
Lee, Eunji [1 ]
Bahn, Hyokyung [2 ]
Noh, Sam H. [3 ]
机构
[1] Seoul Natl Univ, Dept Comp Sci & Engn, Seoul 151, South Korea
[2] Ewha Womans Univ, Dept Comp Sci & Engn, Seoul, South Korea
[3] Hongik Univ, Sch Comp & Informat Engn, Seoul, South Korea
基金
新加坡国家研究基金会;
关键词
Design; Algorithms; Performance; Buffer cache; file system; nonvolatile memory; journaling; reliability;
D O I
10.1145/2560010
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Journaling techniques are widely used in modern file systems as they provide high reliability and fast recovery from system failures. However, it reduces the performance benefit of buffer caching as journaling accounts for a bulk of the storage writes in real system environments. To relieve this problem, we present a novel buffer cache architecture that subsumes the functionality of caching and journaling by making use of nonvolatile memory such as PCM or STT-MRAM. Specifically, our buffer cache supports what we call the in-place commit scheme. This scheme avoids logging, but still provides the same journaling effect by simply altering the state of the cached block to frozen. As a frozen block still provides the functionality of a cache block, we show that in-place commit does not degrade cache performance. We implement our scheme on Linux 2.6.38 and measure the throughput and execution time of the scheme with various file I/O benchmarks. The results show that our scheme improves the throughput and execution time by 89% and 34% on average, respectively, compared to the existing Linux buffer cache with ext4 without any loss of reliability.
引用
收藏
页数:17
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    Ju, Lei
    Jia, Zhiping
    [J]. PROCEEDINGS OF THE 2016 DESIGN, AUTOMATION & TEST IN EUROPE CONFERENCE & EXHIBITION (DATE), 2016, : 942 - 947
  • [2] UniBuffer: Optimizing Journaling Overhead With Unified DRAM and NVM Hybrid Buffer Cache
    Zhang, Zhiyong
    Shen, Zhaoyan
    Jia, Zhiping
    Shao, Zili
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2020, 39 (09) : 1792 - 1805
  • [3] A Unified Write Buffer Cache Management Scheme for Flash Memory
    Shi, Liang
    Li, Jianhua
    Li, Qingan
    Xue, Chun Jason
    Yang, Chengmo
    Zhou, Xuehai
    [J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2014, 22 (12) : 2779 - 2792
  • [4] A Buffer Cache Algorithm for Hybrid Memory Architecture in Mobile Devices
    Oh, Chansoo
    Kang, Dong Hyun
    Lee, Minho
    Eom, Young Ik
    [J]. CLOUD COMPUTING (CLOUDCOMP 2015), 2016, 167 : 293 - 300
  • [5] A Buffer Cache Architecture for Smartphones with Hybrid DRAM/PCM Memory
    Lin, Ye-Jyun
    Yang, Chia-Lin
    Li, Hsiang-Pang
    Wang, Cheng-Yuan Michael
    [J]. 2015 IEEE NON-VOLATILE MEMORY SYSTEMS AND APPLICATIONS SYMPOSIUM (NVMSA), 2015,
  • [6] A Novel Energy-Oriented Reconfigurable on-chip Unified Memory Architecture Based on Cache Behavior Phase Graph
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    Ling Ming
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    Mei Chen
    Wang Huan
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  • [7] Monolithic 3D-Based SRAM/MRAM Hybrid Memory for an Energy-Efficient Unified L2 TLB-Cache Architecture
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