A multiplierless 2-D convolver chip for real-time image processing

This paper proposes a new real-time 2-D convolver chip with no multiplier. Several commercial 2-D convolver chips have many multipliers and existing multiplierless architectures have many shift-and-accumulators to meet the real-time image processing requirement, i.e., the standard of CCIR601. Even though the proposed architecture uses only one shift-and-accumulator, it can meet the real-time requirement. Furthermore, because it controls the input data sequence, the proposed chip does not require row buffers to store two adjacent rows as do commercial chips, and it can further reduce the gate count. The proposed architecture can reduce the gate count by more than 70 and 90% compared to HSP48901 and HSP48908, respectively, and the gate count of the computation block itself by more than 70% compared to existing multiplierless architectures. We have implemented the chip using the Samsung(TM) 0.8 mum SOG cell library (KG60K). The implemented filter chip consists of only 3,893 gates, operates at 125 MHz and can meet the real-time image processing requirement. The proposed architecture is especially suitable for larger size convolutions because of its small gate count.