Polishing in fabrication of superconducting circuits with ramp-edge junctions

A ramp-edge junction was fabricated with 200-nm-thick YBa2Cu3O7-x (YBCO) electrodes and an intermediate insulating layer of 300-nm-thick LaSrAlTaO (LSAT). Extraneous electrode areas are placed on top of their ramps as a result of the fabrication process. The junction exhibited an RSJ-like I-V curve with a swelling or steps depending on the shape of the extraneous electrode areas. The junctions on a 4-mmrectangle chip were polished and the extraneous electrode areas were removed. We obtained quasi-planar junctions with planarized surfaces and base structures composed of YBCO and LSAT. The swelling and steps were explained as results of the resonance of parasitic inductance and capacitance as they disappeared after polishing. The IcRn product did not decrease, which suggests that the junction was not damaged by polishing. We think that polishing will be important in the fabrication of high-T-c superconducting circuits with ramp-edge junctions. (C) 2002 Elsevier Science B.V. All rights reserved.