A Configurable FPGA-Based Traffic Generator for High-Performance Tests of Packet Processing Systems

For the evaluation of high-speed packet processing systems, high performance traffic generators are needed. They have to be configurable to produce various traffic patterns and achieve preferably full Gigabit link utilization. The evaluation of packet processing systems has become a critical task as current open-source-especially software-tools have a lack of throughput and suitable hardware generators are very expensive. Thus, an FPGA-based testing framework containing a traffic generator and a performance monitor, each of them based on an FPGA, was developed. In order to evaluate different packet processing systems, this framework maintains a high level of configurability. Summarized, this paper presents an FPGA-based traffic generator, dedicated to high throughput testing of packet processing systems.