SACR: Scheduling-Aware Cache Reconfiguration for Real-Time Embedded Systems

被引:6
|
作者
Wang, Weixun [1 ]
Mishra, Prabhat [1 ]
Gordon-Ross, Ann [2 ]
机构
[1] Univ Florida, Dept Comp & Informat Sci & Engn, Gainesville, FL 32611 USA
[2] Univ Florida, Dept Elect & Comp Engn, Gainesville, FL 32611 USA
关键词
D O I
10.1109/VLSI.Design.2009.66
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Dynamic reconfiguration techniques are widely used for efficient system optimization. Dynamic cache reconfiguration is a promising approach for reducing energy consumption as well as for improving overall system performance. It is a major challenge to introduce cache reconfiguration into real-time embedded systems since dynamic analysis may adversely affect tasks with real-time constraints. This paper presents a novel approach for implementing cache reconfiguration in soft real-time systems by efficiently leveraging static analysis during execution to both minimize energy and maximize performance. To the best of our knowledge, this is the first attempt to integrate dynamic cache reconfiguration in real-time scheduling techniques. Our experimental results using a wide variety of applications have demonstrated that our approach can significantly (up to 74%) reduce the overall energy consumption of the cache hierarchy in soft real-time systems.
引用
收藏
页码:547 / +
页数:2
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