A 35-GHz Frequency Synthesizer Using Frequency Doubling and Phase Rotating Technology

被引：0

作者：

Yang, Ching-Yuan ^{[1
]}

Chang, Chih-Hsiang ^{[2
]}

Weng, Jun-Hong ^{[3
]}

机构：

[1] Natl Chung Hsing Univ, Dept Elect Engn, Taichung, Taiwan

[2] Ind Technol Res Inst, Informat & Commun Res Labs, Hsinchu, Taiwan

[3] Tunghai Univ, Dept Elect Engn, Taichung, Taiwan

来源：

2013 13TH INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS AND INFORMATION TECHNOLOGIES (ISCIT): COMMUNICATION AND INFORMATION TECHNOLOGY FOR NEW LIFE STYLE BEYOND THE CLOUD | 2013年

关键词：

frequency synthesizer; phase-locked loop; frequency doubler; high-speed divider; VCO;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The paper addresses the design and realization of a high-frequency and wide range frequency synthesizer based on a PLL together with a varactorless LC-type VCO and a push-push frequency doubler. In addition, a high-speed programmable divider using multi-phase selection is employed for channel switching. The proposed circuits were fabricated in a standard 90-nm CMOS process with a chip area of 0.8x1.1 mm2. The PLL dissipates 60 mW at a 1.2-V supply. The measured phase noise of the doubler at 35.28-GHz frequency is -90.42 dBc/Hz at a 1-MHz offset.

引用

页码：266 / 270

页数：5

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