WCET analysis of superscalar processors using simulation with Coloured Petri Nets

被引：7

作者：

Burns, F ^{[1
]}

Koelmans, A ^{[1
]}

Yakovlev, A ^{[1
]}

机构：

[1] Univ Newcastle Upon Tyne, Dept Comp Sci, Newcastle Upon Tyne NE1 7RU, Tyne & Wear, England

来源：

REAL-TIME SYSTEMS | 2000年 / 18卷 / 2-3期

基金：

英国工程与自然科学研究理事会;

关键词：

WCET; superscalar processors; Coloured Petri Nets; modelling;

D O I：

10.1023/A:1008101416758

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Determining a tight WCET of a block of code to be executed on a modern superscalar processor architecture is becoming ever more difficult due to the dynamic behaviour exhibited by current processors, which include dynamic scheduling features such as speculative and out-of-order execution in the context of multiple execution units with deep pipelines. We describe the use of Coloured Petri Nets (CP-nets) in a simulation based approach to this problem. A complex model of a generic processor architecture is described, with emphasis on the modelling strategy for obtaining the WCET and an analysis of the results.

引用

页码：275 / 288

页数：14

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