Improving Power-Delay Performance of Ultra-Low-Power Subthreshold SCL Circuits

被引：14
|
作者：
Tajalli, Armin [1 ]
Alioto, Massimo [2 ]
Leblebici, Yusuf [1 ]
机构：
[1] Swiss Fed Inst Technol, EPFL, Microelect Syst Lab, CH-1015 Lausanne, Switzerland
[2] Univ Siena, Dept Informat Engn, I-53100 Siena, Italy
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2009年 / 56卷 / 02期
关键词：
Source-coupled logic (SCL); subthreshold SCL (STSCL); ultralow-power circuits; weak inversion SCL (WiSCL); COMMUNICATION; OPERATION; LOGIC;
D O I：
10.1109/TCSII.2008.2011603
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This brief presents a technique for improving the power-delay performance of subthreshold source-coupled logic (SCL) circuits. Based on the proposed approach, a source-follower buffer stage is used at the output of each SCL stage. Analytical results confirmed by measurements in 0.18-mu m CMOS technology show an improvement by a factor of as high as 2.4 in power-delay product (PDP). It is also shown that the proposed technique can be used for implementing subthreshold ultra-low power SCL logic gates with a better power and area efficiency, compared to the traditional SCL subthreshold circuits. An optimized approach is proposed to improve the power efficiency of ultra-low power STSCL library cells.
引用
收藏
页码：127 / 131
页数：5
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