A Gate Voltage Sensing Ripple Reduction Control Technique for Switched-Capacitor DC-DC Converters

A gate voltage sensing based control technique for switched-capacitor (SC) DC-DC converters with low output voltage ripple and input peak currents is presented. The technique implements two control loops. An inner loop regulates the output voltage to virtually eliminate output voltage ripple and significantly reduce the input peak current. An outer control loop uses a control signal from the inner loop to implement switching frequency modulation to ensure high efficiency across a wide output current range. The proposed technique is implemented in a 28 nm FD-SOI CMOS process as a 2:1 series-parallel SC converter for 1:8V input voltage, 500mV to 850mV output voltage and 40 mu A to 6mA output current. Across this range, the proposed technique shows an output voltage ripple reduction from 49:7mV to 3:0mV at 40 mu A and from 23mV to 2:5mV at 6mA with no discernible effect on the power-stage efficiency.