MSGCROC - an ASIC for High Count Rate Readout of Position Sensitive Microstrip Gas Chambers for Thermal Neutrons

被引:0
|
作者
Brogna, Andrea S. [1 ]
Buzzetti, Siro [4 ]
Dabrowski, Wladyslaw [6 ]
Fiutowski, Tomasz [6 ]
Gebauer, Burckhard [5 ]
Mindur, Bartosz [6 ]
Schmidt, Christian J. [3 ]
Schulz, Christian [5 ]
Soltveit, Hans K. [1 ]
Szczygiel, Robert [6 ]
Trunk, Ulrich [2 ]
Wiacek, Piotr [6 ]
机构
[1] Heidelberg Univ, Inst Phys, D-69120 Heidelberg, Germany
[2] DESY, D-22607 Hamburg, Germany
[3] Gesell Schwerionenforsch mbH, D-64291 Darmstadt, Germany
[4] Politecn Milan, INFM, 1-20133 Milan, Italy
[5] Helmholtz Zentrum Berlin Materialien & Energie Gm, D-14109 Berlin, Germany
[6] AGH Univ Sci & Technol, Fac Phys & Appl Comp Sci, PL-30059 Krakow, Poland
关键词
DETECTORS;
D O I
暂无
中图分类号
R8 [特种医学]; R445 [影像诊断学];
学科分类号
1002 ; 100207 ; 1009 ;
摘要
In this paper we report on the development of an ASIC for readout of position sensitive neutron detectors based on low-pressure Micro-Strip Gas Chambers with solid composite Gd-157/CsI converter. Global counting rates of 10(8) cps for a detector area of 25x25 cm(2) covered with 400x400 strips requiring 2 ns time resolution for coincidences of signals from X- and Y-strips set very demanding requirements for the ASIC performance. The MSGCROC ASIC employs a novel readout ASIC architecture, in which time stamps of timing signals are buffered in the digital form on channel basis. The X- and Y-signals are matched in an external FPGA-based circuitry according to their time stamps. In parallel with time measurements also signal amplitudes are measured and buffered on the chip. The signal amplitudes are used to discriminate between the signals from neutrons and from background X-rays, as well as to calculate centre of gravity for events with signals spread over 3 to 4 strips in case of MSGC detectors. The preamplifier-shaper circuits in the MSGCROC can handle both polarities of the input signals so that it can be used for the cathode as and the anode readout. Furthermore, in other to cope with various gas amplification factors resulting in different input charges, a switchable gain stage has been implemented in the preamplifier with five relative gain steps from 1 to 20. The readout of both buffers is performed via a token-ring based multiplexer, which ensures data sparsification and full zero suppression so that only non-zero data are transmitted to an external FPGA-based front-end board including fast ADCs. The analogue data is read out via a single differential link at a rate of 32 MHz. The digital data is read out via a parallel 8-bit LVDS bus at a rate of 128 MHz.
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页码:757 / +
页数:2
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