The state-of-art and future trends in testing embedded memories

被引：29

作者：

Hamdioui, S ^{[1
]}

Gaydadjiev, G ^{[1
]}

de Goor, AJV ^{[1
]}

机构：

[1] Delft Univ Technol, Fac Elect Engn, Comp Engn Lab, NL-2628 CD Delft, Netherlands

来源：

RECORDS OF THE 2004 IEEE INTERNATIONAL WORKSHOP ON MEMORY TECHNOLOGY, DESIGN AND TESTING | 2004年

关键词：

D O I：

10.1109/MTDT.2004.1327984

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

According to the International Technology Roadmap for Semiconductors (ITRS 2001), embedded memories will continue to dominate the increasing system on chips (SoCs) content in the next years, approaching 94% in about 10 years. Therefore the memory yield will have a dramatical impact on the overall defect-per-million (DPM) level, hence on the overall SoC yield. Meeting a high memory yield requires understanding memory designs, modelling their faulty behaviors in the presence of defects, designing adequate tests and diagnosis strategies as well as efficient repair schemes. This paper presents the state of art in memory testing including fault modeling, test design, Built-In-Self-Test (BIST) and Built-In-Self-Repair (BISR). Further research challenges and opportunities are discussed in enabling testing (embedded) memories, which use deep submicron technologies.

引用

页码：54 / 59

页数：6

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